Capricorn Jumper Link Settings

 

PL11508 Fader Controller
PL11510 / 510A Meter MotherBoard
PL11511 Console Node
PL11519 Graphics Node
PL11521 Concard (bottom)
PL11522 I/O (top)
PL11523 I/O (bottom)
PL11525 Filter (bottom)
PL11527 DRC (bottom)
PL11529 Neve Storage Node
PL11533 Neve Tape Node
PL11536 Neve Analog Madi
PL11543 16 Channel AES Card
PL11545 Neve Digital Madi
PL94314
PL94317
SPN815-102 Fader Controller
SUN820-168 Tape Node
SUN820-180 Storage Node (bottom)
SUN820-185 Storage Node (top)
SUN820-187 Analog Madi
SUN820-207 Digital Madi
SUN820B209 CXS Rack Micro


Fader MotherBoard (PL11508)                    
LK1(off)
Meter MotherBoard (PL11510/PL11510A)
LK1(on) 28MHz clock - jumper must be fitted
LK2(off) NOT USED
LK3(on) ATE test jumper - ON during normal operation, but removed for GenRad test
LK4(on) ATE test jumper - ON during normal operation, but removed for GenRad test
Strip/AFU Node (PL11511)
LK1 47R Must be fitted or board will not boot
LK2(on)  
LK3(R/H of 3) Switches Brightness frequency
LK4(off) GenRad test jumper (NOT USED)
LK5(STRIP) OFF for a STRIP NODE
LK5(AFU) ON  for an AFU NODE
Graphics Node (PL11519)
LK1 (lower of 3)
LK2(off) GenRad test jumper - NOT USED
LK3(on)
LK4 47R
LK5 (lower of 3)
LK6(off) GenRad test jumper - NOT USED
LK7(on) 36MHz clock jumper - must be fitted
Concard 'B' Half (PL11521)
LK1(off)
LK3 47R
LK4(off)
I/O Card 'A' Half (PL11522)
LK1(on) LK10 (off)
LK2(on) LK11(off)
LK3(off) LK12(off)
LK4(on) LK13(off)
LK5(on)    
LK6(on) LK16(off)
LK7(on) LK17(off) 47R
LK8(on)    
LK9(off) LK23(off)
I/O Card 'B' Half (PL11523)
LK1(on) LK15(on)
LK2(off) LK16(on)
LK3(off) LK17(on)
LK4(on) LK18(on)
LK5(on) LK19(on)
LK6(off) LK20(on)
LK7(off) LK21(on)
LK8(on) LK22(on)
LK9(on) LK23(on)
LK10(on) LK24(on)
LK11(on) LK25(on)
LK12(on) LK26(on)
LK13(on) LK27(on)
LK14(on) LK28(on)
Filter Card 'B' Half (PL11525)
LK1(off)
LK3 47R
LK4(off)
DRC Card 'B' Half (PL11527)
LK1(off)
LK2(off)
LK3(off) 47R
Storage Node 'B' Half (PL11529)
LK1(on)
LK2(off)
LK3(on)
LK4(on)
LK5(on)
LK6(on) 47R
LK8(off)
Tape Node (PL11533)
LK1(on)
LK2 47R
LK4(off)
RIBBON CABLE P3 to P4
Analog Madi (PL11536 / PL11536A)

Default settings are - Processor boot from PROM and  AES wordclock equalisation NOT ENABLED
LK1(on) Enables Madi TX
LK2(off) Processor boot source ICE
LK3(on) Processor boot source PROM
LK4(on) AES Sync EQ Bypass - Should consider leaving OFF  to enable AES EQ for  cable runs over 75 metres - see tan9602
LK5(off) Selects Madi Fail Source along with LK6
LK6(on) Selects Madi Fail source along with LK5
LK7(off) Watchdog enable
16 Channel AES Card (PL11543)

Default settings are - Diagnostics disabled for ALL channels.and AES equalisation ENABLED for ALL channels
LK0(off) Install for Diagnostic mode channels 0,1
LK1(off) Install for Diagnostic mode channels 2,3
LK2(off) Install for Diagnostic mode channels 4,5
LK3(off) Install for Diagnostic mode channels 6,7
LK4(off) Install for Diagnostic mode channels 8,9
LK5(off) Install for Diagnostic mode channels 10,11
LK6(off) Install for Diagnostic mode channels 12,13
LK7(off) Install for Diagnostic mode channels 14,15
LKA0(off), LKB0(off) Install to bypass equalisation for channels 0,1
LKA1(off), LKB1(off) Install to bypass equalisation for channels 2,3
LKA2(off), LKB2(off) Install to bypass equalisation for channels 4,5
LKA3(off), LKB3(off) Install to bypass equalisation for channels 6,7
LKA4(off), LKB4(off) Install to bypass equalisation for channels 8,9
LKA5(off), LKB5(off) Install to bypass equalisation for channels 10,11
LKA6(off), LKB6(off) Install to bypass equalisation for channels 12,13
LKA7(off), LKB7(off) Install to bypass equalisation for channels 14,15
Digital Madi (PL11545)

Default settings are - Boot from PROM and AES wordclock sync equalisation disabled
LK1(on) AES +ve wordclock sync EQ bypass - Install to bypass EQ
LK2(off) NOT USED
LK3(on) AES -ve wordclock sync EQ bypass - Install to bypass EQ
LK4(on) Processor INT
LK5(on) Processor INT
LK6(on) Processor INT
LK7(on) Processor INT
LK8(on) Watchdog enable
LK9(off) Processor boot from ICE
LK10 (on) Processor boot from PROM
LK11(off) Madi fail source select  as LK12
LK12(on) Madi fail source select as LK11
LK13(on) MADI TX enable
Lower AFU (PL94314)
LK1(off)
Mid Monitor (PL94317)
LK1(R/H of 3)
Fader Controller (SPN815-102)

view orientation as card would be in the System
J16  
J17  
J18  
J19  
J20  
J21  
Tape Node (SUN820-168)
LK1 (on) Processor startup
LK2(L/H of 3) Interrupt 3 source (backplane or IDC header P8)
LK3(L/H of 3) Interrupt 0 source (backplane or Link interrupt)
LK4 (off) Ring circuit
LK5 (on) Link 1 link speed (on=10Mbits/sec, off=20Mbits/sec
LK6(on) Link 0 link speed (on=10Mbits/sec, off=20Mbits/sec
LK7(on) General purpose read?
Ribbon Cable P3 to P4 ?
Storage Node (bottom) (SUN820-180)

view orientation as card would be in the System
J5(Left of 3) BRA(9) Enable
J6 (on) IP Bus start enable
J7 (on) OP Bus start enable
J8 (on) PSB Bus start enable
Storage Node Top (SUN820-185)
J8 (OFF) AES Sync EQ Bypass (default EQ enabled with jumper OFF)
J9 (OFF) AUX Ring Enable (default OFF to reduce EMC)
J10 (OFF) AUX Ring test mode with jumper fitted
J20 (OFF) Transputer Link speed select (OFF for 20MBits/sec)
J22 (OFF) Transputer Link speed select (OFF for 20MBits/sec)
J29 (OFF) MAIN Ring test mode with jumper fitted
Copper Analog Madi (SUN820-187)
J5 AES EQ bypass (jumper on)
J6 +VE AES OP 110R enable
J7 -VE AES OP 110R disable
J8 Shunt resistor (110R) AES +VE OP to AES -VE OP enable
J9 Boot from ROM
J10 Boot from ICE
J11 Shunt resistor (130K) AES +VE IP to AES -VE IP enable
J12 Madi transmit enable
J26 AES IN +VE through 620R resistor
J27 AES IN +VE through 100N cap
J28 Kick watchdog enable
Fibre Analog Madi (SUN820A187)

DAR for back of FIBRE module

Jumper settings same as SUN820-187 above
Copper Digital Madi (SUN820-207) and Fibre digital madi (SUN820A207)
J2 Boot from ICE
J3 Boot from ROM
J8 Kick watchdog enable
J9 MADI Tx Enable
J10 AES EQ bypass (jumper on)
J11 AES Screen to GND
J12 AES IN +VE through 100N cap
J13 AES IN +VE through 620R resistor
J14 Shunt resistor (130K) AES +VE IP to AES -VE IP enable
J15 -VE AES OP 110R enable
J16 +VE AES OP 110R enable
J17 Shunt resistor (110R) AES +VE OP to AES -VE OP enable
 

 
SUN820B209 CXS Rack Processor
J1 R/H of 3 ON
J2 OFF
J3 OFF
J4 OFF
J5 (jumper on)